[hpsdr] My DFC Delusion?

[Scott Traurig]

Bryan,

The only architecture I've ever seen for the "DFC" approach has the raw ADC
samples being moved to a GPU via PCIE. No processing of the raw ADC samples
at all in the FPGA. The same is true for the DAC data stream, just raw DAC
data coming into the FPGA from the PCIE interface. In addition to this, no
more audio CODEC in the radio hardware, all audio I/O will be via VAC or
equivalent. The FPGA basically only does general housekeeping and PCIE data
transfer. That is the entire point of the architecture, to eliminate to the
maximum extent possible any FPGA code, to make that code extremely simple
and stable, and to be able to utilize smaller, less expensive FPGAs. This
way 90% of what is currently being done in the FPGA and which requires
Verilog coding and all the other FPGA folderol (timing closure, etc.) can
now be done more simply in C code in a GPU.

73,

Scott/w-u-2-o

On Fri, Nov 23, 2018 at 6:48 PM Bryan Rambo <bryanr at bometals.com> wrote:

>
> Hi All,
>
> I know I'm starting to lose it, no doubt of that, but I swear I remember
> the early (very early) concept of DFC being one where the big, full 60MHz
> FFT was done in the FPGA before being sent over PCIe to the computer.  I
> seem to remember having seen a lecture by NR0V or VK6PH where this was the
> original DFC architecture, ie to do almost all the heavy lifting in the
> computer (and/or video proc), but to let the FPGA crunch out the FFT before
> going over to the PC.
>
> Or do I need to check myself into the looney bin?
>
> 73, Bryan W4WMT
>
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