[hpsdr] AngeliaLite project

[Marc OLANIE]

Hi Oleg 
Same questions as Helmut's. I saw you developed your board with Kicad. Do you intend to publish the whole hardware projetc under Github ?
I also had the same reaction : it's a nice competitor to the 14 bits Red Pitaya project. Particularly if it's an open hardware (and software) platform. 
I imagine you considered using a 14b/125MSPS adc. The cost is definitely not the same :- ( I also hope you will present it for the next SDR accademy 
Thnks for your very promizing dev 
Marc f6itu


-----Message d'origine-----
De : Hpsdr <hpsdr-bounces at lists.openhpsdr.org> De la part de Helmut Oeller
Envoyé : samedi 15 février 2020 09:14
À : 'Oleg Skydan' <olegskydan at gmail.com>; hpsdr at openhpsdr.org
Objet : Re: [hpsdr] AngeliaLite project

***** High Performance Software Defined Radio Discussion List *****

Hi Oleg,

many thanks for your information and the interesting HPSDR  derivative description. Evidently you have spent a lot of time and brainpower into this project. So I'm wondering what your intention for the future is. Do you want to market the boards? As you certainly know 'low cost' competition already exists with the 'Red Pitaya' for example. Due to the low sampling rate your product can not cover the 50 MHz band.
Anyway, this year we are planning another HPSDR workshop/meeting on the HAM RADIO 2020 Friedrichshafen. Feel free to introduce and demonstrate your development. It's a good place to meet experienced people of the SDR ambience.

73, Helmut, DC6NY


-----Ursprüngliche Nachricht-----
Von: Hpsdr <hpsdr-bounces at lists.openhpsdr.org> Im Auftrag von Oleg Skydan
Gesendet: Freitag, 14. Februar 2020 17:58
An: hpsdr at openhpsdr.org
Betreff: [hpsdr] AngeliaLite project

***** High Performance Software Defined Radio Discussion List *****

Hi, All!

Some time ago I designed an SDR module for my other projects and experiments. The module has two RX channels (with DVGA and 14bits AD9255 synchronized ADCs) and one TX output (with 14bits AD9744 DAC). There are also Cyclone 4 FPGA EP4CE22E22, configuration memory and all necessary components for clocking and power it up. The ADCs are clocked at 77.76MHz and the DAC is clocked at 155.52MHz by the low noise ABLJO-155.52MHz VCXO which is locked from the 10MHz internal TCXO or external reference.

My friend asked if it can be turned into the OpenHPSDR compatible transceiver. So, I made it :-). It is two board construction which supports OpenHPSDR protocol v2 (but with 100Mb/s Ethernet). It is not a complete transceiver - it lacks RX/TX filters and TX power amplifier.

The FPGA firmware is based on the OpenHPSDR Angelia code, the NCO code is from the HermesLite2 project. There were many changes in the code to fit 4
DDCs/2 ADC support into the relatively small and low pin count EP4CE22E22 FPGA, some changes were required because of the different ADC/DAC sample rates, some modules are completely new.

The second board contains Ethernet PHY, standard ALEX, OC, keyer and PTT interfaces, four analog inputs, diagnostic LEDs, switching 5V regulator (so it can be powered from the single 12V supply). There is also STM32F072 MCU on the second board (it helps to save FPGA logic/pins).

You can find more information here:
https://github.com/UR3IQO/AngeliaLite

BTW, I have fixed one bug in the Angelia DHCP code - if Ethernet cable was unplugged and plugged in again the board failed acquiring IP address using DHCP (at least with my TP-Link Archer C7/OpenWrt router). The problem was in address renewal - if it fails DHCP client should start REBIND completely restarting DHCP procedure and it should send DHCPREQUEST using multicast address (the original code uses unicast address and fails to obtain DHCP address). See code/comments for details.

73!
Oleg UR3IQO 

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