[hpsdr] AngeliaLite project

[Oleg Skydan]

Hi Marc,

> Same questions as Helmut's. I saw you developed your board with Kicad. Do 
> you intend to publish the whole hardware projetc under Github ?

I am going to publish board files for the mainboard.

I have no plans to make SDR module open hardware currently, but it is 
possible I will do it later.

> I imagine you considered using a 14b/125MSPS adc. The cost is definitely 
> not the same :-(

There should be no substantial benefits going to 125MSPS ADC with 122.88MHz 
clock. It will be able to work with 384kSPS and possible higher sample rates 
at DDC output (but I am not sure the design with sufficiently good filters 
for the higher sample rates will fit in the FPGA).

Also it may have better MDS/BDR with low "attenuator" settings cause it 
should be possible to suppress DVGA noise in the 2nd Nyquist zone. But 
benefit will be barely observable (I expect it will be 1..2dB).

50MHz as I wrote before is already there (with 77.6MSPS ADC).

73!
Oleg UR3IQO