[hpsdr] FW: Penelope Issue

[steve@coastaldatasystems.com]

Meant to send to the list...

-----Original Message-----
From: steve at coastaldatasystems.com <swestfisher at coastaldatasystems.com> 
Sent: Thursday, September 19, 2024 8:26 AM
To: 'Helmut Oeller' <oeller at freenet.de>
Subject: RE: [hpsdr] Penelope Issue

I'm not surprised at the lack of response, now that I'm retired I have a lot
more time to devote to these old projects.
I can program it either through the Ozy board or JTAG, but when I cycle the
power the FPGA doesn't load the program. 
The issue is that I don't believe the EPCS4SI8N (U8) is working. The FPGA
doesn't store the program, it has to load on every power up and in my case
that isn't happening.
If you have a working one could you look at U8 - just above and a little
left of the FPGA and let me know if the angled edge of the chip is closest
to the back edge of the board?
There are no marks on the chip I have so I had to assume that pin 1 is on
the side of the angle on the chip. This isn't even clear to me from the
datasheet.


Steve West-Fisher
N4IK

-----Original Message-----
From: Hpsdr <hpsdr-bounces at lists.openhpsdr.org> On Behalf Of Helmut Oeller
Sent: Thursday, September 19, 2024 5:50 AM
To: hpsdr at lists.openhpsdr.org
Subject: Re: [hpsdr] Penelope Issue

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