[hpsdr] FPGA power management

[Lyle Johnson]

>> As far as I understand your circuit the LD1117 is delivering the VCCIO and the FAN1112
>> does the 1.2Volt VCCINT (or core voltage). This means that VCCIO will be up before the
>> core voltage (just opposite to what Altera recommends).

> Yep, you are correct.  I was thinking upside down.

I suspect that while the 3.3V VCCIO will be *rising* before the core, 
the core will reach its 1.2V operating voltage when VCCIO is around 
+2.4V (worst case with 1A load, more likely to be around +1.8V or so), 
long *before* the VCCIO is at its target level.  Not sure if this 
completely violates Altera's recommendations...

73,

Lyle KK7P


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