[hpsdr] OZy Speed Test

[Philip Covington]

Hi all,

I was able to achieve 38 MBytes/S transfer rate between OZY and my
computer at work (Dell P4 3.4 GHz dual core).  This is writing data to
EP6's FIFO by holding SLWR low and clocking in bytes until I get a
full flag.

Writing 1 byte at a time to EP6's FIFO (meaning cycling SLWR
asserted/unasserted and enabling/disabling the data bus) I was able to
achieve 9-10 MByte/S.

Flopping back and forth between reading FIFO EP2 and writing FIFO EP6
is even slower (like in the EP2_LED test).  Having to select the FIFO
with the FIFO_ADR lines causes a huge penalty in transfer speed. The
FIFO_ADR lines have settling times that are longer than one IFCLK
period.

If anyone wants to try the transfer speed test you need to load
fifo_test.rbf and run fifo_test.exe (both can be found in SVN).  The
OZYV1FW08042006-1.hex file should not be used with JANUS yet because I
set the FX2 clock speed back up to 48 MHz from 24 MHz.  If you do load
this firmware revision you'll notice that the FPGA upload times are
halved (as expected).

73 de Phil N8VB