[hpsdr] Atlas Bus Question/Comment

[Lyle Johnson]

> Maybe I'm looking in the wrong place but I couldn't find any description of
> the Atlas bus signals other than power and some serial bus and JTAG
> definitions.

Those are all that are defined at the moment.  We're using FPGAs and 
CPLDs to interface between things so we can evolve the signal paths as 
the project grows, without locking ourselves into something early on.

The bus is primarily a means to communicate between boards, as opposed 
to putting high speed memory on one board and a CPU on another, for 
example.  I expect there will be some fairly wide, reasonably fast 
paths, but those will likely be on the order of 16 to 24 bits and under 
100 MHz.

> For example, if one wished to design a board to plug into the
> Atlas bus, what is the protocol for bus arbitration,

There is none.  One master is enough, I hope :-)

> board identity,

Dallas 1-wire using a DS2431 on each board.

> bus control signals, etc etc?

There are none, yet.

73,

Lyle KK7P


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