[hpsdr] Horton LO

[Philip Covington]

On 6/16/06, pvharman at arach.net.au <pvharman at arach.net.au> wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> Chris,
>
> The DDS provides the fine frequency steps. Since we can get away with 10kHz
> steps I don't see why a DDS is required.
>
>
> Bob,
>
> I was looking at a canned GHz oscillator, not multiplying up.  A 2.4GHz DIP
> VCO when divided down should give a very respectable phase performance.
>
> The ADF4153 Fractional_N chip works up to 4GHz.
>
> 73's Phil...VK6APH

I looked at doing a division scheme a while ago:

My thoughts at the time were to use a VCO in the frequency range that
a CPLD could be used as a programmable divider:

--------------------------------------------------------------------------------------------
Re: My QSE

--- In softrock40 at yahoogroups.com, "Leon Heller" <leon.heller at b...> wrote:
> I might design a PLL
> for generating the 4x signal, later. They have some advantages over
a DDS.
>
> 73, Leon

I've looked at using a Minicircuits 100-200 MHz VCO and National PLL
to get full coverage of 160-10 meters. For example:

Low vco/divide High vco/divide
1.800 121.600/64 2.000 128.000/64
3.500 120.000/32 4.000 128.000/32
7.000 114.400/16 7.300 116.800/16
10.000 161.200/16 10.150 162.400/16
14.000 113.400/8 14.350 114.800/8
18.068 144.944/8 18.168 145.344/8
21.000 169.800/8 21.450 171.600/8
24.890 199.520/8 24.990 199.920/8
28.000 115.400/4 29.700 118.800/4

So if you have a johnson /4 counter, and 4 selectable /2 FFs in front
of the johnson counter your will get full coverage of 160-10m with a
VCO running in the range of 100-200 MHz. The step size of the PLL can
be 10kHz or more and the software NCO will fill in the steps.

73 de Phil N8VB

-------------------------------------------------------------------------------

This could be extended up into the microwave with the appropriate
fixed dividers to get the range down to something a programmable
divider in a CPLD would handle.

The question that I have not worked out is how much the dividers add
to the jitter/phase noise?  I saw an earlier post where John S.  said
that certain dividers were better than others.

I also wonder if the frequency range is within something that a CPLD
could handle, how much jitter is added by division in the CPLD.  I am
not talking about using the PLLs or anything in the FPGA/CPLD... just
a programmable/selectable divider.

73 de Phil N8VB

 1150461017.0