[hpsdr] Horton LO

[Lyle Johnson]

> If we take the 500 MHz high quality oscillators and do a johnson counter 
> to produce four signals at 125 MHz to drive the capacitors in the QSD,  
> we can then feed each of the 125 MHz signals into four equal length 
> divider chains.  With 16 bit dividers,   we get 2.5 KHz resolution.  If 
> we find we cannot put the 16 bit counters in a CPLD,

CPLD or FPGA creating four instances of a 16-bit programmable divider 
with 50% output duty cycle is easy.

What we need is an FPGA or CPLD with four "zero delay, high drive" clock 
lines inside the part.  I suspect the phase noise we'll get from the 
division process switching threshold uncertainties will be fairly small, 
and adequate for our purposes.

The Max II device from Altera for example, has speed grades rated to 
clock at 300 MHz and has exactly four global clock lines.  The smallest 
device, like we're using in Janus, has 240 FPGA logic elements, so we'd 
have 60 for each programmable divider.  We'd need fewer, giving us some 
to use as the input program register to steer the dividers.  $8 or so 
for the fast parts.

The smallest Cyclone II device, like Phil is using in Ozymandias, has 8 
global networks, 4608 logic elements, and is available in speed grades 
to 260 MHz.  The EP2C5T144C7() is only $15.30 in singles.

I think if the jitter in these parts is acceptable, all we need is the 
VP oscillator and the 500 MHz Johnson counter.  The jitter properties of 
the divider will be important, but of course that'll be divided 
down/averaged by the 16-bit programmable counter.  Need to find the 
right way to implement that counter...

73,

Lyle KK7P




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