[hpsdr] Horton LO

[Robert McGwier]

I am worried about the phase noise of the VCO being useful.  Can we get 
any kind of part number, data sheet for a VCO of interest?  The PLL 
design is critical to the performance here.    Starting with -100 dBc at 
N*10 kHz and losing 6*log_2(N)  dB of that with a divider of  and 
winding up with (say) -120 dBc will not be suitable.

Bob



Philip Covington wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> On 6/17/06, John B. Stephensen <kd6ozh at comcast.net> wrote:
>   
>> The disadvantage of dividing down a 1-2 GHz VCO is that the ECL dividers
>> have a -145 to -155 dBc/Hz broadband noise floor, depending on which
>> dividers are used. 100-200 MHz will work with CMOS CPLDs, which should have
>> a lower noise floor. Some CPLDs will work to 300-400 MHz.
>>
>> 73,
>>
>> John
>> KD6OZH
>>     
>
> I wonder if this is a problem with the AD clock distro chips (links
> were posted yesterday)?  They will take up to a 1.6 GHz clock and
> divide by a selectable 1 through 32.  That would get us down into the
> range that a FPGA/CPLD could handle - providing we had a VCO running
> in the 500-1000 MHz range or 600-1600 MHz range...
>
> Or can we just come up with a low phase noise 100-200 MHz VCO?
>
> 73 de Phil N8VB
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>   


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