[hpsdr] Horton LO

[John B. Stephensen]

The clock distribution chips are ECL or CML, which is similar. If you can do
a division of 8-16 at the end of the chain in CMOS there will be no poblem.
Otherwise, starting at a lower frequency is btter. If you analyze the
wideband VCOs, you'll find out that the resonator Q is 30-50. You can do a
lot better at 200 MHz.

73,

John
KD6OZH

----- Original Message ----- 
From: "Philip Covington" <p.covington at gmail.com>
To: "John B. Stephensen" <kd6ozh at comcast.net>
Cc: "Phil Harman" <pvharman at arach.net.au>; "High Performance Software
Defined Radio Discussion List" <hpsdr at hpsdr.org>
Sent: Saturday, June 17, 2006 14:45 UTC
Subject: Re: [hpsdr] Horton LO


> On 6/17/06, John B. Stephensen <kd6ozh at comcast.net> wrote:
> > The disadvantage of dividing down a 1-2 GHz VCO is that the ECL dividers
> > have a -145 to -155 dBc/Hz broadband noise floor, depending on which
> > dividers are used. 100-200 MHz will work with CMOS CPLDs, which should
have
> > a lower noise floor. Some CPLDs will work to 300-400 MHz.
> >
> > 73,
> >
> > John
> > KD6OZH
>
> I wonder if this is a problem with the AD clock distro chips (links
> were posted yesterday)?  They will take up to a 1.6 GHz clock and
> divide by a selectable 1 through 32.  That would get us down into the
> range that a FPGA/CPLD could handle - providing we had a VCO running
> in the 500-1000 MHz range or 600-1600 MHz range...
>
> Or can we just come up with a low phase noise 100-200 MHz VCO?
>
> 73 de Phil N8VB


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