[hpsdr] [OZY] Initial OZY Schematic Posted For Review and Comments- May 10, 2006

[Lyle Johnson]

Hello Phil!

> At this point I have 32 lines from the FPGA that will go to headers. 

HP/Agilent has a spec for a 20-pin 2x10 0.1" male header for their logic 
analyzers that gathers a 16-bit "bus".  They have since moved on to even 
higher density stuff, but if the pins could be arranged in this way, it 
makes it easier for those of use with such Logic Analyzers handy :-)

Top view looking down on PCB to male header pointing up towards viewer:

   2   4   6   8  10 12 14 16 18 20
   1   3   5   7   9 11 13 15 17 19

Pin  Function

  1   +5V *from Analyzer* do not connect!
  2   DO NOT CONNECT
  3   CLOCK
  4   D15
  5   D14
  6   D13
  7   D12
  8   D11
  9   D10
10   D09
11   D08
12   D07
13   D06
14   D05
15   D04
16   D03
17   D02
18   D01
19   D00
20   GND

73,

Lyle KK7P


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