[hpsdr] What can we do with 2 cards

[Philip Covington]

Hi Bill,

If we agree to forgo the Logic Analyzer/Debug Port(s) and also agree
that we will never expect to add external SRAM then I can drop the I2C
IO stuff and provide somewhere around 32 I/O off the OZY.  I think you
can do all 3 below then.  Then we need to discuss how to
protect/buffer those lines in a way to allow all 32 to be inputs,
outputs, or a combination of both.

I am leaving soon this morning, and on the drive to/from home I will
be thinking more about this.

73 de Phil N8VB


On 5/13/06, Bill Tracey <bill at ewjt.com> wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> When we started down this path with the Xylo I think one of the
> configuration goals we had was:
>
>          1. Sound Card replacement
>          2. Ultra Low Latency CW input
>          3 .SDR 1000 Parallel Port Control
>
> As we morphed to HPSDR my hope was that this configuration could be done
> with two cards - Audio (Janus) and USB/FPGA (Ozy)
>
> At the moment it looks like we may only be able to do #1 with 2 cards.  We
> might be able to do #1 & #2 if we can get low latency CW keying via I2C I/O
> via FX2.    We certainly cannot do #3 with just 2 cards.  At the moment on
> the Xylo prototypes we've got PTT/DOT and DASH coming thru FPGA pins and
> their state gets integrated into the audio data stream going to the radio,
> giving very low latency..  Doing CW via I2C via FX2 may have sufficiently
> low latency, not sure of this.  I'd assume we'd have to read from an FX2
> USB endpoint to get the status of the ports -- anyone know if one can do a
> blocking read waiting for the state of the I2C ports to change from the PC
> -- hate the idea of having to poll the USB port at a hi rate for good CW
> performance.       I don't think we can do SDR 1000 parallel port control
> with the I2C expander as it takes 17 (D0-7, C0-3, S3-S7)  lines, also not
> clear to me  how quickly we can and need to wiggle those lines to program
> the DDS in the SDR 1000 when going via an I2C.
>
> One idea to get back to doing dot/dash directly thru the FPGA is to go
> through the Janus.  It looks like there are 4 unused I/O on the Janus
> CPLD.  Could we add some protection circuitry on the Janus to 2 of those
> lines and configure the CPLD to put those sigs on the Atlas bus.   Maybe
> add 3 more pins to the 0.100 unbalanced audio connector?
>
> I that's not  viable, is there space for protection circuitry for 2 lines
> on the Ozy  and a 3 pin connector?  Could we jumper the configuration of
> the FPGA serial port such that it's either tied to the level converter or
> the external connector?
>
> Just some late night thoughts -- trying to find a way to get a little more
> function into a 2 board setup.
>
> Regards,
>
> Bill (kd5tfd)
>
>
>
>
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