[hpsdr] New RF Digitizer

Ahti Aintila oh2rz.sdr at gmail.com
Tue Nov 14 02:22:12 PST 2006


Nyall,

Thank you for your explanation. Obviously HPSDR plans to use the
16-bit LTC2208 with specified 130 MHz sampling. If there are no faster
replacements for the AD6620, so possibly some FPGA should be used
instead. How much that would help?

73, Ahti OH2RZ

On 14/11/06, Nyall Davies <nyalldavies at ukonline.co.uk> wrote:
>
> COMPARISON OF SDR-IQ with HPSDR
> The signal noise ratio of the fast AD converters does not allow the full use
> of all the bits. The extra bits in the AD should mean that the quantization
> loss in the AD can be ignored - it should provide its own dither noise.
>
> The picture of the SDR-IQ shows that it uses the AD6620 which comprises the
> digital mixer and set of CIC filters. The processing gain the AD6620 is such
> that 23 bits are required at its output
> I cannot see what AD it uses but we have to assume that it is the AD6645.
> This part has a S/N ratio around 74dB
> It states that the sampling is done at 67MHz (the max spec of the AD6620)
> If we are using the LTC2207 sampling at 100MHz - it has a quoted S/N of 78.2
> dB so we are better due to the AD SN by 4.2dB
> If we sample at 100 MHz we gain 10 log(100/67) dB of processing gain =1.739
> dB
>
> So we can expect a performance 4.2 +1.7 = 5.9dB better than the SDR-IQ
>
> It has been suggested to me that we Linear tech can supply a device to
> sample at higher rates say 150MHz so we may, depending on the S/N of this
> device, be able to gain another 1.7dB
>
> Nyall G8IBR
>
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