[hpsdr] New RF Digitizer

[Philip Covington]

On 11/14/06, Philip Covington <p.covington at gmail.com> wrote:
> Hi all,
>
> I guess the SDR-IQ is supposed to be a less expensive version of the
> SDR-14 according to what they were saying on the SDR-14 yahoo group.
>
> SDR-IQ Comments:
>
> 1. The price looks much better vs the $1200 for SDR-14.  It appears to
> be a nice compact board.
>
> 2. They are using the Atmel AT91SAM7S256 microcontroller with USB 2.0
> full speed interface.  Note that the USB on the Atmel operates at full
> speed (12 MSPS) not high speed (480 MSPS).  This limits the real time
> bandwidth they can move over the USB interface.  It appears that 192
> kHz is the upper limit for the SDR-IQ.  The largest packet size the
> the AT91SAM7S256 supports is 64 bytes which is also a limiting factor.
>  It appears that the 4 endpoints share a 392 byte FIFO in the ATMEL
> chip.  The 12 MSPS is not much of an improvement over the SDR-14 which
> uses a FTDI USB chip.  A CPLD with the Cypress CY7C68013A  (FX2) would
> have given USB high speed connectivity.   The Atmel and the FX2 are
> almost exactly the same cost.  A MAX II CPLD would add about $4. I
> assume the designers of the SDR-IQ were more familiar with
> microcontrollers than FPGAs/CPLDs?
>
> 3. I assume they have some SRAM or external FIFO for non-real time
> spectrum scans wider than the 192 kHz that the USB interface can
> handle.  This allows a wide bandwidth to be sampled into on board
> memory and to be read out slowly by the microcontroller to USB.
>
> HPSDR Mercury Comments:
>
> 1. FPGA vs DDC chips:  The DDC function can be done in either a FPGA
> or a dedicated DDC chip like the AD6620 that the SDR-IQ uses.  The
> AD6620 handles 14 bit data and 67 MSPS which makes it unsuitable for
> use with the LTC2208.  Two possibilities are the AD6636 or the TI
> GC5016 DDCs.  Both are BGAs with 256/252 balls.  The AD6636 can  take
> 16 bit inputs up to 150 MSPS and the GC5016 can take 16 bit inputs up
> to 160 MSPS.  The GC5016 is actually a DDC/DUC combined where the
> AD6636 is a DDC only.  Since both are BGAs we could also go the route
> of using a larger FPGA in BGA package to implement the DDC functions.
>
> 2. The AD6636 has four or six channels depending on part suffix.  That
> means that the input from the LTC2208 can be processed by any or all
> of the 4/6 channels and the output of these 4/6 channels can be
> interleaved over the USB interface.  For example, you could have the
> first channel covering 500 kHz of 160 meters, the second covering 500
> kHz of 80 meters, the third covering 500 kHz of 40 meters, and the
> fourth covering 500 kHz of 20 meters all at the same time over the
> high speed (480 MSPS) USB interface we use in OZY.
>
> 3. Using a large enough FPGA we could implement similar functionality
> to the AD6636.  how large is something that has to be determined.  We
> are definitely into BGA packages for this, I'm afraid.
>
> 4.  The AD6636 has a digital AGC block for each channel on the input
> data and after each channels for the output data.  Whether this
> provides enough dynamic range is still not determined.
>
> 5.  Since the OZY is the interface to the PC we will able to move a
> much wider bandwidth in real time over USB to the PC than the SDR-IQ
> is able to do.  Theoretically, it could be >20 MHz.
>
> 6.  The big questions to be answered is whether the AD6636 (or GC5016)
> is suitable for Mercury or whether we should use a larger BGA packaged
> FPGA to implement the DDC functions (and how large to get equivalent
> or better functionality to the AD6636?).
>
> Phil N8VB
>

Please note that all of the above comments about the SDR-IQ is only
speculation on my part based on what I saw on the RF Space website.

Phil N8VB

 1163515792.0