[hpsdr] Mercury

[jeff millar]

Lyle Johnson wrote:
>
> Since these are flip-flops and not MUXes, I don't understand their use. 
>   Can't we just run the ADC output directly to the FPGA and to the DDC?
>   
ADC performance depend critically on minimizing the digital switching 
currents flowing on the digital pins (to minimize noise). Designs always 
buffer the output unless the lines run straight to a single device (that 
has low capacitance inputs).
> Do we need a larger/different family FPGA for more resources or speed to 
> implement a DDC?  I'm concerned that the ADI part may not have a long 
> life.  And of course, it is BGA...  If we are prepared to use BGA, we 
> can get a very fast, very dense FPGA.
>   
If an ASIC can do the job, then it will have less size and power 
consumption than an FPGA from the same technology era, because ASICs 
have more optimized designs. The gap is about 10:1 in base cost. Another 
way to say it...It takes 5 years of Moore's Law advancement for an FPGA 
to equal an optimal ASIC in size, power and base cost. The FPGA has an 
advantage when no ASIC exists for the available ASICs don't fit the 
requirement very well.

The AD6636 has 5 channels and most of today's SDR applications only 
require one, so an FPGA gains some advantage by implementing just what 
the SDR needs.

Maybe a different part in the AD66xx family that costs less, such as the 
AD6620??

jeff, wa1hco


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