[hpsdr] Penelope - Verilog block diagram

[Eric Blossom]

On Sun, Apr 01, 2007 at 01:29:37PM +0800, Phil Harman wrote:
> ***** High Performance Software Defined Radio Discussion List *****
> 
> I've upload a block diagram to the Wiki of the Verilog code that I am 
> developing for  Penelope.
> Having not documented like this before I would appreciate feedback on how 
> useful such diagrams will be to those that may wish to understand, or modify 
> the code themselves, later on.
> 
> < 
> http://hpsdr.org/wiki/index.php?title=PENELOPE#PENELOPE_-_Companion_Exciter_to_Mercury >
> 
> The code is still under development and will be in  SVN ASAP.
> 
> 73's Phil...VK6APH
> 

Definitely useful.

I do have a question.  You're feeding this complex baseband, right?
If so, then what's the purpose of the add_IQ block?  I would have
thought that you would be feeding either the I or Q output of the
cordic to the DAC.

73 Eric K7GNU

 1175443950.0