[hpsdr] Mercury: LTC2209

[Philip Covington]

On 4/20/07, Jason A. Beens <jbeens at sensetechnologies.com> wrote:
> > from Phil...
> >It is not trivial to come up with a clock generation and distribution
> >scheme to drive two LTC2209 ADCs.
>
> I like the term "not trivial"... I would probably choose less polite
> words to describe the effort.
>
> Performing a high speed digital layout with a wide parallel interface
> can be really annoying.  I prefer to use serial interfaces when
> possible, but at these sample rates the serial interface would have to
> be very high bandwidth.  To move data at the maximum rate of the LTC2209
> would require a serial link with a bit rate of more than 2.7
> Gbits/second.
>
> The raw data throughput is within the ability of PCI Express, and
> possibly some of the SerDes stuff used for gigabit Ethernet (like in
> back plane operations).  There are some nifty FPGAs that incorporate
> these functions as hardware, but I have not seen a PCI Express ADC, yet
> to mate up with the high performance FPGA serial interface.
>
> There are folks on this list who seem to be in tune with what the
> semiconductor manufacturers are currently producing... Is such an ADC on
> anyone's radar?
>
> I would be surprised if the answer is yes, but I am curious.
>
> Jason Beens
> KB0CDN

The LTC2208 has either CMOS or LVDS outputs.   It would be no problem
to go LVDS into the FPGA (provided you use one with enough IO pins).
The LTC2208 dissipates quite a bit more power when using LVDS.  We
chose to use the CMOS interface with randomizing (since the
derandomization can be easily done in the FPGA).

The problem is not handling the data output of the two ADCs.  The
"non-trivial" part is handling the encode clock generation and
distribution to the two ADCs.   It is non-trivial to design a very low
phase noise encode clock at those sample rates.  It is also
non-trivial to keep the encode clocks and RF front ends feeding the
two ADCs balanced through the entire 0-170 MHz range.

If you throw enough money at it, it can be done - but I don't think
most people interested in a Mercury are going to want to pay $1000+
for a single board.

73 Phil N8VB

P.S. Speaking of PCI Express, I am right now working on a project that
uses a Stratix II GX with PCIe on one side and SFP (at 2.5 Gbps) fiber
interfaces on the other.  Unfortunately the particular Stratix II GX
FPGA (90K+ LEs) costs > $2000 alone and has 1508 BGA balls!

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