[hpsdr] Verilog vs VHDL

[Rick Eversole]

k5nwa wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> Which is more user friendly? I'm trying to decide between Verilog and 
> VHDL for a FPGA project and wanted some opinions on the subject 
> before I go out and spend some money on books. The project will 
> involve mostly processing of I/Q audio streams and some video display 
> control, so a big issue will be math processing.
>
> I'm leaning heavily towards Verilog since it seems less wordy than 
> VHDL, and there are some in this group that are familiar with it.
>
> Any thoughts?
>   

Yet another answer from one who has used both languages for 17 years.
I have worked for Cadence, Mentor Graphics and now Synopsys.
I get paid to know both languages. I have written thousands of lines of 
code in both.
I know 29 programming languages (including Verilog and VHDL). I prefer 
Verilog
and in recent years it appears that VHDL is finally falling behind. 
While Verilog is
eing upgraded to "SystemVerilog", the VHDL camp is finding it hard to 
find funding to
update the latest LRM. "SystemVHDL" may not actually be needed but as it 
stands now
I do not think it will ever happen.

 Verilog is C like (Prahbu Goel and Phil Morby [creators of the 
language] liked  C)
Not strongly typed. S
ubject to coded race conditions.
But fastest to learn and tuned toward hardware better than VHDL.
Verilog simulates faster than VHDL
Verilog has gate level primitives (AND, NAND, NOR etc) as part of VHDL.
A useful value type system is part of  base Verilog.

VHDL is ased upon ADA (Many of the same people who specified the ADA 
language were involved
  in the creation of VHDL).
It is a strongly typed language.
It is very hard to code a race condition.
It  takes longer to learn.
More typing is involved to accomplish the same task in VHDL as compared 
to Verilog.
VHDL simulates slower than VHDL (2-4x slower is typical even for gate 
level simulations)
VHDL does not have gate primitives. You have to code them in RTL tyle. 
The "VITAL" specification
   provides a set of gate primitves that map to Verilog primitives.
VHDL does not have a logic system that is useful for gate designs. You 
need the "standard logic 1164"
   package which ships with any real VHDL simulator. Like Vital this is 
a layer on top of the base language.


Over the years I have seen side by side test with "expert" VHDL users 
and Verilog users. In general the
Verilog users out perform the VHDL users. There are lots of issues with 
how these tests are constructed
but my experience shows that Verilog is fasest to get the design done 
but VHDL designs often are easier
to maintain and update.

Each language has advantages. The new SystemVerilog language will remove 
all but VHDL's strong typed
"advantage". Whether strongly typed is a real advantage is a debate for 
another time.

In practice, it is not possible to translate between the languages. 
Semantics are incompatible. You have to
completely recode in a non-mechanical process. Translators can help but 
30% recode is not uncommon.
(unless you have pure structural code then translation can be almost 100%)

Rick "The Rhino" N6RNO
> Cecil
> KD5NWA
> www.softrockradio.org  www.qrpradio.com
>
> "Blessed are the cracked, for they shall let in the light."  
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