[hpsdr] Mercury V2 FPGA code upgrade - beta testers wanted.

[Phil Harman]

All,

Background:

When Phil, N8VB, designed the Atlas bus he had the foresight to include 
a JTAG chain.  The idea was that in the future (i.e. now!) we will need 
to update the code in the various FPGAs/CPLDs/Flash memory on the 
boards that comprise HPSDR.

We have been very fortunate that the code that TAPR installed in Janus 
and Penelope during manufacture has been relatively stable and we have not needed to 
update any code to date.

This is about to change since we have a number of active developers 
working on the Mercury FPGA code and I'd like to take advantage of the 
ideas and features they have added as soon as possible.

Beta Testing:

I propose that we do the Mercury upgrade in 3 stages.

Stage 1:  For experienced users who have the necessary skills and 
equipment to quickly beta test the new code.

Stage 2:  For intrepid experimenters who are willing to install the new 
Mercury code that has been validated in Stage 1. No hardware tools will 
be required but some software will need to be installed and configured 
on your PC.

Stage 3: For everyone else.  Either an automatic code upload or a 
"click here" application.

For Stage 1 beta testers I've added a directory  called Mercury V2 in SVN here

< svn://206.216.146.154/svn/repos_sdr_hpsdr/trunk/Mercury V2 

Load the Mercury.pof  file into the EPCS16 and give us feedback. 
Also load the latest PowerSDR that supports the new features developed
by Bill, KD5TFD, using SVN from 

< svn://206.216.146.154/svn/repos_sdr_windows/PowerSDR/branches/kd5tfd/PennyMerge/bin/Release >

Existing Mercury users may also want to use this latest version of PowerSDR -  in this case just leave the sampling
rate at 192kHz for now. 

The new code has been contributed by  Darrell Harmon, Cathy Moore, Gerd 
DJ8AY, Bill KD5TFD  and Alex VE3NEA.  If you, like me, are learning Verilog then have 
a look at Alex's code - simply brilliant.

If you are a suitable Stage 1 beta test candidate then you are not going to need 
any further instructions.

The new features include:

- selectable sample rates of 48/96/192kHz
- removal of the roll off at the edges of the bandscope
- removal of the need to DC correct the DSP chain output
- >100dB of alias signal rejection outside the bandscope passband
- smaller, faster code
- improvement  to the order dependence of HPSDR cards on the Atlas bus


For Stage 2 we are going to provide code that loads into the Ozy board 
that makes it simulate an Altera USBBlaster.  Using a free command line 
program you will be able to load the required code into the Mercury 
EPCS16 flash memory. Some software will need to be installed on your PC 
and you will need to follow step-by-step instructions.  More details 
regarding Step 2 later.

For Stage 3 we hope to fully automate the process such that the updated 
code is automatically loaded when starting an application or PowerSDR.

Over to the Stage 1 beta testers!

73's Phil... VK6APH
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