[hpsdr] Fixed Saw Oscillators (FRANCIS CARCIA)

[Hans Summers]

Frank

>  The VCSOs have an active phase shifter in the loop to pull the oscillator. I would like to know how a DDS can multiply a clock by 8 and not degrade close in phase noise? Frank

The DDS internal PLL clock multiplier DOES degrade phase noise. For
example look at the AD9912 datasheet, page 11 figure 13 vs figure 12.
Figure 12 is 1GHz ref clock direct (no PLL multiplication inside the
DDS). Figure 13 is 83.33MHz ref clock internally multiplied by 12. The
difference in phase noise is roughly 10dBc/Hz whether you look at 1kHz
offset or 10kHz, and whether you look at 399MHz output or 99MHz
doesn't make much difference: still 10dBc/Hz.

73 Hans G0UPL
http://www.hanssummers.com