[hpsdr] protocol example

[dk4xp at hoffmann-hochfrequenz.de]

On Fri, 04 Dec 2009 09:01:45 +0000, you wrote:

>***** High Performance Software Defined Radio Discussion List *****
>
>One of my concerns is that the actual spec will cost $100 plus another 
>$25 for the  Link Layer Protocol fromo VITA.  Does anyone have a copy of 
>these? What are the restrictions on distribution?  I am sure we would 
>not be allowed to put a copy on the web site for anyone to get access to.
>
> From the papers I have read it would seem this protocol is for receive 
>only.  I may be wrong but not having paid out the $125 I have not seen 
>the full specification.

By googling for the name of the author of the conference paper and 
the title of the paper on the Pentek site I stumbled across this as
answer #5 :

<http://www.digitalif.org/images/VRT_49.0_draft_0.21_approved.pdf>


While it's not the official standard and as such useless for real 
products, it should be close. There is no remark that it could
not be copied.

I'm working on an open bus system somewhat similar to Wishbone, but
with absolutely maximum re-use of wires and pipelining to keep the
cycle time fast. Logical and physical address & data path widths are 
independent and there will be some support for UDP and streaming.
The draft let me conclude at least that a 64K block size is enough.

I have bought the Vita FMC mezzanine board standard and plan to do
a SDR mezzanine board, as FMC is supported by the new Xilinx Virtex6
and Spartan6 development boards. You cannot get the FPGA chips for
the price of the demo boards unless you buy 1000s, so this should 
make sense.

USB/audio/Ethernet/JTAG is already provided on the demo boards, 
so I could concentrate on dynamic range/jitter/phase noise.


Ideas / proposals welcome!

regards, Gerhard DK4XP

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