[hpsdr] optimum Tx image rejection in DUC?

[Bob McGwier]

It isn't present because the signal presented to FPGA in the Mercury, 
QS1R and similar devices is real.  It is a single channel A/D feeding 
the processing.  The downconverter (DDC) is a nearly perfect mixer and 
downsampler.

Bob


Ken N9VV wrote:
> ***** High Performance Software Defined Radio Discussion List *****
> 
> Hi, I am learning about the benefits of DDC for receive where there is 
> no issue of "receiver image rejection" because it is always taken care 
> of in an optimum mathematical manner in the FPGA.
> 
> Is the same thing true of a DUC transmitter? is Tx image rejection 
> handled by the FPGA in a mathematically optimum manner?
> 
> Image rejection in the QSD type rigs has always been quite a challenge. 
> In the DDC/DUC rigs, no one every mentions it. Does image rejection for 
> both Rx and Tx just disappear in the FPGA?
> 
> tnx,
> de Ken N9VV
> _______________________________________________
> HPSDR Discussion List
> To post msg: hpsdr at openhpsdr.org
> Subscription help: 
> http://lists.openhpsdr.org/listinfo.cgi/hpsdr-openhpsdr.org
> HPSDR web page: http://openhpsdr.org
> Archives: http://lists.openhpsdr.org/pipermail/hpsdr-openhpsdr.org/


 1261886916.0