[hpsdr] Call for Comments and Discussion - OzyII

[Phil Harman]

Hi Larry,

This should be quite straighforward. I did a similar thing when developing 
Mercury by interfacing an LTC2208 evaluation board to the 20 pin IDC header 
on Ozy.

If you make a small PCB with an IDC header and PHY etc that will fit on the 
20 pin header on Mercury then you should be able to quickly test the idea.

That would work as a standalone receiver and since you could remove all the 
Atlas bus interface code would leave plenty of room for the PHY interface.

When developing Mercury as above I was able to get the complete receiver 
plus USB interface in the Ozy C2 FPGA - a bit of a tight fit but it worked 
as a single board receiver just fine.  Given the Mercury FPGA is a C3 you 
should have plenty of room.

If you have a PHY chip in mind to test this idea then please let me know 
since it would perhaps save duplication of effort.

73's Phil...VK6APH


----- Original Message ----- 
From: "Larry Gadallah" <lgadallah at gmail.com>
To: "hpsdr" <hpsdr at openhpsdr.org>
Sent: Monday, July 27, 2009 3:05 AM
Subject: Re: [hpsdr] Call for Comments and Discussion - OzyII


***** High Performance Software Defined Radio Discussion List *****

2009/7/21 Eric Blossom <eb at comsec.com>:
>
> With the current board stack there's pretty much no way to generate
> this much data given the low rate of the interconnect. If the ADC,
> FPGA, and gigE are all on the same card, it starts to make sense.
>

This leads to an interesting question: How hard would it be to
retrofit an Ethernet PHY to a Mercury card and add the Ethernet
interface logic into the existing FPGA? Is there enough
space/horsepower available? Presumably, this would result in a
standalone Mercury card, and you could run a number in parallel if you
wanted to.

-- 
Larry Gadallah, VE6VQ/W7                          lgadallah AT gmail DOT com
PGP Sig: 917E DDB7 C911 9EC1 0CD9  C06B 06C4 835F 0BB8 7336
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