[hpsdr] Call for Comments and Discussion - OzyII

[alex]

verilog is modular i think.

wasn't the whole idea of pluging a merc into the chip supposed to be a 
test for ozy2. like when merc was developed as an ozy with an adc added, 
this is a merc with an interface added

also, emailing phil harman and hpsdr, then phil will get the email 
twice, i find that that can be quite annoying but that might just be me

> ***** High Performance Software Defined Radio Discussion List *****
>
> 2009/7/27 Phil Harman <phil at pharman.org>:
>   
>> Hi Larry,
>>
>> This should be quite straighforward. I did a similar thing when developing
>> Mercury by interfacing an LTC2208 evaluation board to the 20 pin IDC header
>> on Ozy.
>>
>> If you make a small PCB with an IDC header and PHY etc that will fit on the
>> 20 pin header on Mercury then you should be able to quickly test the idea.
>>
>> That would work as a standalone receiver and since you could remove all the
>> Atlas bus interface code would leave plenty of room for the PHY interface.
>>
>> When developing Mercury as above I was able to get the complete receiver
>> plus USB interface in the Ozy C2 FPGA - a bit of a tight fit but it worked
>> as a single board receiver just fine.  Given the Mercury FPGA is a C3 you
>> should have plenty of room.
>>
>> If you have a PHY chip in mind to test this idea then please let me know
>> since it would perhaps save duplication of effort.
>>
>>     
>
> How about one of the same PHYs being proposed for Ozy II? Perhaps then
> the associated FPGA code could be reused for Ozy II also, if it was
> crafted carefully to make it modular (btw - I'm a FPGA/Verilog savant,
> I have no idea if that's possible or not).
>
>   


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