[hpsdr] Problem: PowerSDR glitch,

[Gerd Loch]

Hi Tokio,

I suppose that the glitches you observed are timing problems with the FPGA
code. 
I tried to get Mercury-EU with firmware 3.0 (which is about the same as 6.0)
running with sampling clock 196 MHz as I do quite a long time with
Mercury-EU firmware 2.5.
I did not succeed and there was no answer on the reflector.
Finally I reduced the no. of receivers to 1 and now the firmware was
running. So it was not a mistake in changing the code to the different clock
speed 196 MHz.
Using Timing Analyses in Quartus I found that there is a problem with
C122_clk not meeting the requirements. Even it does not fully meet the
requirements for the normal clock speed of 122.88MHz. It is running in
practice because Timing Analysis is considering worst case conditions but it
is not far off from the limit. 
I am just now investigating how far this timing problem can be reduced or
solved with different optimizing techniques including different speed grades
for the FPGA and even considering the advantages of Stratix FPGA's.

Gerd, DJ8AY