[hpsdr] Problem: PowerSDR glitch,

[Tokio Endo]

Hi Gerd,

Yesterday I replied to the help from Joe, K5SO, that the glitch disappeared,
but I noticed again the glitch with Mercury firmware 29(2.9a).
I think this is not due to the ATOM processor performance. The phenomenon is
very sporadic.

If the problem comes from FPGA code found by Timing Analysis, and if
upgarding FPGA is the sole means, the situation is quite serious.
As far as I remember I didn't notice problem like this before upgrading of
Mercury firmware.

The "Glitch" I heare on my Mercury is not something like spike noise, very
very short interruption without any noise, like instantenous fade out of
auido, then the auido comes back normal. This is very very short period, but
it is annoying.

Backward Mercury firmware to 2.5 may clear the problem, I'll try.

Tokio Endo
ja1cca

-----Original Message-----
From: hpsdr-bounces at lists.openhpsdr.org
[mailto:hpsdr-bounces at lists.openhpsdr.org]On Behalf Of Gerd Loch
Sent: Sunday, October 24, 2010 11:42 PM
To: hpsdr at lists.openhpsdr.org
Subject: Re: [hpsdr] Problem: PowerSDR glitch,


***** High Performance Software Defined Radio Discussion List *****

Hi Tokio,

I suppose that the glitches you observed are timing problems with the FPGA
code.
I tried to get Mercury-EU with firmware 3.0 (which is about the same as 6.0)
running with sampling clock 196 MHz as I do quite a long time with
Mercury-EU firmware 2.5.
I did not succeed and there was no answer on the reflector.
Finally I reduced the no. of receivers to 1 and now the firmware was
running. So it was not a mistake in changing the code to the different clock
speed 196 MHz.
Using Timing Analyses in Quartus I found that there is a problem with
C122_clk not meeting the requirements. Even it does not fully meet the
requirements for the normal clock speed of 122.88MHz. It is running in
practice because Timing Analysis is considering worst case conditions but it
is not far off from the limit.
I am just now investigating how far this timing problem can be reduced or
solved with different optimizing techniques including different speed grades
for the FPGA and even considering the advantages of Stratix FPGA's.

Gerd, DJ8AY



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