[hpsdr] Phase synchronization of multiple Mercury boards at startup

[Joe Martin K5SO]

All,

I have successfully implemented the approach suggested below by using  
Ozy and dual Mercury boards as a first try since the Ozy code already  
has the Janus reset function in it.  Modifying the Mercury FPGA code  
to look at the Atlas C2 line and use that line to hold the DSP  
functions in reset until released by Ozy seems to have cured the issue  
of random phase startup between multiple Mercury boards.   It's not  
completely perfect but it's very, very, very close!  After  
establishing a greater than 70 dB null on single signal input to both  
Mercury receivers then power cycling the Atlas bus numerous times the  
system comes back up with the null in place to within a few dB or so  
every time.  Much, much better than before when it would come up with  
no null at all without completely re-adjusting phase after power  
cycling Atlas.

I'll now modify the Metis firmware to do the same.  The mod is  
straightforward and, to keep firmware versions at a minimum, I think  
this addition should be included in the general Metis firmware  
releases too since this synchronization does not affect single Merc  
operation (of course), occurs only at startup after a power down of  
Atlas, and is totally invisible and undetectable by the user.

This will make the physical direction calibration in my steering  
programs actually meaningful regardless of whether the system has been  
shut down many times since the calibration was performed.  Wonderful!

That cures the issue that John N8UR kindly brought up yesterday.

Thanks for that great bit of insight (and memory, hihi!), Phil.

73,  Joe K5SO


On Sep 22, 2011, at 11:09 PM, Phil Harman wrote:

> Hi Joe,
>
> Just thinking about the issue of the phase relationships between each
> Mercury board being different each time you power cycle.
>
> I think we may be able to fix this.
>
> At the moment each FPGA decides when to send data to the Atlas bus  
> once it
> comes out of reset.  This will depend on how long it takes for the  
> FPGA to
> load from the flash etc.
>
> If you look on the Atlas bus with a 'scope then I would expect the  
> 'data
> available' signal from each Mercury to vary in time with respect to  
> the
> others each power cycle.
>
> What we could do is send a master reset to all Mercury boards via the
> Atlas bus so that all the DSP code in each FPGA starts at the same  
> time.
>
> Perhaps worth a look if you have time.  There is already a reset pin  
> on
> the Atlas bus (C2) that is used by Janus.
>
> 73 Phil...VK6APH
>


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