[hpsdr] ADC Question

[Bill Tracey]

Hmmm ... 122.88Mhz was chosen after we'd built a few boards with a 
125 MHz sampling clock on the ADC and ran into issues with the PC 
side code (PowerSDR, CW timing in this case) assuming an exact 48, 
96, or 192 khz sampling rate.   I dorked around with all sorts of 
resampling and other hacks to get it right and finally threw in the 
towel and insisted that the clock rate we used be exactly dividable 
down to 48khz.   (One of the few instances where a software guy 
insisted on a fix in hardware and got it)!

In short, you have to rejigger the firmware to present 48/96/192 khz 
samples to the PC.  I have a suspicion it's may not be trivial to do 
a non integral decimation in the firmware.

Regards,

Bill

At 01:32 PM 7/24/2012, Larry Gadallah wrote:
>***** High Performance Software Defined Radio Discussion List *****
>
>
>I'm building a second Mercury board up from scratch, and I'm 
>considering using a different ADC, from the same family as the 
>LTC2208; the LTC2207 which is pin-compatible with the LTC2208 and 
>offers slightly better ENOB and SFDR but at a little slower sample 
>rate (105 MSPS versus 130, and yes, you would lose some or all of 
>the 6M band in doing this).
>
>Since the stock Mercury uses the 122.88 MHz clock to drive the ADC, 
>I presume that this clock would have to be slowed down to something 
>less than 105 Mhz to work with the LTC2207. My question is: What 
>else would this affect? Could one card on the Atlas bus run at it's 
>own clock rate compared to the rest? Would the firmware still work 
>asynchronously, or does it have the 122.88 Mhz clock "hardcoded" in places?
>
>Thanks,
>--
>Larry Gadallah, VE6VQ/W7                          lgadallah AT gmail DOT com
>PGP Sig: B5F9 C4A8 8517 82AC 16B6  02B6 0645 69F0 1F29 A512
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