[hpsdr] Questions re: FPGA firmware

[Joe Martin K5SO]

As is always the case, volunteers to make the code better are most welcome!  

73, Joe K5SO

On Oct 30, 2012, at 10:18 AM, <kirk at hdlexpress.com> wrote:

> The main reason this happens is because the Timing Analysis failed at build time.  It needs to be looked at and corrected.  FPGAs don't fail unless they aren't meeting timing analysis, are out of temp specs, have signal loading or other specs that are being violated.  In this case the best bet is timing analysis wasn't met during the build.
> 
> Kirk Weedman KD7IRS
> -------- Original Message --------
> Subject: Re: [hpsdr] Questions re: FPGA firmware
> From: Joe Martin K5SO <k5so at valornet.com>
> Date: Tue, October 30, 2012 8:50 am
> To: John Marvin <jm-hpsdr at themarvins.org>
> Cc: hpsdr at lists.openhpsdr.org
> 
> ***** High Performance Software Defined Radio Discussion List *****
> 
> Hi John, 
> 
> To add to Alex's response here are a few additional comments: 
> 
> 3) FPGA space and FPGA performance both, I think. It has been observed that when running with 100% loading of the FPGA (i.e., using 100% of the logic resources) can under some circumstances lead to timing problems and erratic behavior so care must be taken and careful testing must be performed when using heavy FPGA loading. Hermes v1.8 uses 67% of the logic resources and so avoids the issues sometimes observed with heavy FPGA loading.
> 
> 
> 73, Joe K5SO
> 
> 

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.openhpsdr.org/pipermail/hpsdr-openhpsdr.org/attachments/20121030/f73cb88e/attachment-0004.htm>