[hpsdr] filtering options in FPGA

[k3it]

 Does anybody know how big of an effort would be to modify the current
Hermes firmware to send the RX streams after the CIC filters and exclude
all FIR processing?   I'd like to run an experiment with implementing a
decimating FIR filter on the PC.

For example I'd like CIC decimate to 384k in FPGA and then CFIR decimate by
4 on the PC to get 96k finished spectrum.  is there anything wrong with
this approach?

I want to do this for two reasons
- get feet wet with Verilog
- see how much FPGA space can be recovered by moving part of the processing
to the PC

-- 
73! Vasiliy K3IT
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