[hpsdr] New Hermes FPGA code

[Phil Harman]

All,
A new version of Hermes FPGA code V2.7 is available from here:
http://openhpsdr.org/download.php
This fixes a bug where the receive frequency was in error by approximately 1/2 Hz.  Thanks to Mike, KF4BQ, for locating this, his explanation follows this email.
Please note that this update is for Hermes using Alex boards only. Apache Labs will release an updated version for ANAN radios shortly.

73 Phil...VK6PH 


I was playing with the FPGA code and noticed a few things:
1) each 1Hz step is about d35 steps of the C122_sync_phase_word
2) when using Powersdr I noticed that almost all freqs seemed to be off 
about 1/2Hz high; compared to phase lock sig gen.
3) verified this 1/2 Hz error using instantiated logic analyzer in 
Quartus, and comparing calc values
example: at 10Mhz the hand calc phase word should be d349525333.3
the program calcs d349525333 and adds M3 resulting in d349525350 (1/2 Hz 
error now).
1Hz up or down is a 35D change in value.

Looks like a change was made in the last versions of the code adding M3 
(d1172812403). This ends up adding about d17 steps to the 
C122_sync_phase_word. The code was introduced to help since the freq 
was always rounded down. The M3 value should actually be 1000000h = 
d16777216 which would fix this error of always rounding down.

With the M3 value changed: I see the calculated sync_phase_word is 
properly rounded. This effectively added 1/2 step to the 
sync_phase_word (not 1/2 Hz) for the truncation step.

I have changed the M3 value and can see this is a huge difference in the 
orig FPGA code calc. The freq is now selected within 1/35 Hz (maybe 
1/70 with new M3 value). The phase display is now very hard to see move 
!! Probably good enough for direct FMT measurements with this change.

Hope the FPGA team can change the M3 value in the next release. (change 
from d1172812403 to d16777216 in Hermes.v ).

I was going to made more improvements, but this change is about all that 
is needed.

73, Mike Collins KF4BQ

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