[hpsdr] openHPSDR at the forefront of SDR development

[Steven B. Dick]

 Phil, as you indicated, The skills to write, debug and maintain FPGA code
is only available via a small percentage of software engineers, or
enthusiasts, in comparison to those able to write code for PC based
hardware. This has been a major problem in industry for years, as the cost
per "line of code" is much higher for firmware vs. software for code
development and maintenance, on the order of a factor of perhaps 10 to 1 for
FPGA firmware vs. software written in a high order language.  Note that
tools such as MATLAB can be used to develop FPGA code directly rather than
hand coding verilog or VHDL code but are not low cost tools.

Another approach to consider is the newly emerging FPGA vendor support of
high order "graphics" programming languages for their latest "System on a
chip" FPGAs. Both Altera and Xilinx are now beginning to support the OpenCL
programming language for their FPGAs using their latest toolsets. OpenCL is
not proprietary vs. CUDA which is tied in with NVIDIA. CUDA is more mature
and has a more extensive set of available libraries and a larger user
community however. Although programming with OpenCL on an FPGA vs. a
graphics chip using multiple graphics processing engines requires different
programming approaches to take best advantages of the underlying hardware
resources, this may be a way to program for "System on a chip" FPGAs,
strictly in software though maintining a mix of hardware and software
resources, including multiple ARM processors. 

Regards. "Digital Steve", K1RF   

-----Original Message-----
All,

I'm delighted to be able to report that we have been able to develop, to
proof-of-concept stage, a new SDR architecture.

Current SDRs use the software equivalent of zero IF techniques, i.e. DDC,
in order to provide (multiple) receivers.   Whist this is quite effective,
much of the initial DSP work is done using FPGAs, or a combination of FPGA
plus dedicated DSP chips and microprocessors, rather than totally within
the PC.

As more complex features are added, the size and complexity of the FPGA
and DSP code increases. The skills to write, debug and maintain this code
is only available via a small percentage of software engineers, or
enthusiasts, in comparison to those able to write code for PC based
hardware.

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