[hpsdr] Timing Closure Field Guide

[AD0ES]

Hi,

I have been slowly dipping my toes into the SDR pool, have a mercury rcvr setup functioning now.  Excited about the
direction new development is taking, especially in the area of moving more of the work from FPGA to a general class
cpu/gpu.  Next step for me is to setup with the tools necessary to write FPGA/gpu/openCL code.

I spent some time on the Altera(?) site and went away totally confused.  Are there tools available allowing one to
design/write/compile FPGA code for these beasts without paying license fees or BEING CONNECTED to the net while using?
I have no internet  access at home and need a non-inet solution.

If someone could provide a cookbook list of where/how to get the tools I believe it would get more people started down
this path.

tia,
Steve AD0ES

On Aug 26, 2014, at 1:59 PM, Joe Martin K5SO wrote:

> ***** High Performance Software Defined Radio Discussion List *****
> 
> All, 
> 
> In an effort to assist in making the timing closure tasks associated with OpenHPSDR firmware development less intimidating and easier for beginners to participate I have prepared a PDF document that describes a standardized procedure that I use for the task.  The document may be downloaded from


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