[hpsdr] DFC Sampling Frequency?

[John Laur]

I do not know any of the particular implementation details, but I do know
that the sampling frequency for the DFC work is limited by gigabit
Ethernet. 61.44 meg is chosen because it's the best compromise between
fitting into gigabit ethernet and being an easy 1/2 decimation from the
real 122.88 samplerate. At 61.44MHz * 16 bits that is 983mbps of raw ADC
data.

Raw ethernet frames (with a proper L2 header) have a 38 octet/frame
overhead. With a 1500 byte payload the frame size is 1538 bytes. At
61.44mhz 16 bit samples, the raw datarate with 1500 MTU is 1008mbps. With
Jumbo frames (MTU 9000) the overall datarate is 988 mbps. So 61.44Msps at 16
bits can only just fit into Gig-E (at least with careful handling on the PC
side)

Since Hermes Lite uses only a 14bit ADC its theoretical bandwidth in DFC
could be reduced, however performing the expansion of packed 14bit values
into byte aligned memory on the host might be rather expensive. Phil has
maybe already considered this question because the ANAN-10e uses the
LT2208-14 which is also only 14 bit. I would assume that the alignment
could be done on the GPU with relative ease since packing/unpacking bit
values is a fairly common thing to do in computer graphics. So using 14bit
packed values you can send up to 70.217MHz 14 bit samples in the same
ethernet bandwidth. I do not think that the DFC process itself cares much
about the actual samplerate though. So long as the GPU is powerful enough
to do the FFT you should be in business.

For Hermes-Lite you have the problem of needing a higher frequency LO to
achieve good 10m performance, but this may compromise what you can do with
DFC. At the proposed LO frequency of 73.728MHz you would have to decimate
each sample to 13 bits to stay within the limits of gig-e. Or you might be
able to do a 6/5 decimation in the FPGA to get to 61.44Msps. If you can do
the latter, you could emulate the wireline DFC protocol exactly. You could
also change the transport to USB3 or similar, but that would make extra
work.

73, John K5IT


On Sun, Apr 12, 2015 at 10:24 PM, Steve Haynal <steve at softerhardware.com>
wrote:

> ***** High Performance Software Defined Radio Discussion List *****
>
>
>
> In Phil's original announcement of direct Fourier conversion (DFC) radio
> experiments he mentioned that the target sampling frequency was 61.44 MHz,
> or half of the Hermes' original 122.88 MHz. In a recent thread regarding
> FFTs, Phil mentioned:
>
> "This FFTs the entire 0-30MHz spectrum using a 16 bit ADC sampling at
> 74Msps."
>
> What is the target sampling frequency for DFC, or is it a moving target?
> Also, where is the best place to find information about the DFC
> experiments? We are working on the next revision of the Hermes-Lite, and
> although we are not doing anything with DFC, we don't want to exclude the
> possibility for the future.
>
> 73,
>
> Steve
> KF7O
>
>
>
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