[hpsdr] FW: SBC Inforce 6410

[Terry Fox]

Thank you for your concerns Graham.  Laying out what is expected is always a good thing!
I would welcome others to check out the RP.  I’ve been playing with one for over six months now, and am still impressed with the cost vs abilities as an SDR.  It’s not a Hermes-killer, but I don’t expect it to be.

As regards to point 2, it already has Nyquist filters that unfortunately limit the RP to about 50MHz (I’ve checked).  I would like to bypass them for subsampling.

Pavel is handling the 125 MHz vs 122.88 MHz by resampling.  He was going to try the CIC filter up/down resampling, I don’t know what the latest is.  I’m more of the opinion that the oscillator should be changed out, but doing that may be beyond some amateur’s abilities.

I believe it is an eight-layer board.  This thing was designed by some smart guys playing with particle accelerators.  I don’t really buy into the “lab instrument” usage, due to the rather poor software (so far) and lack of front-end attenuators/amplifiers.

As Helmut pointed out, the RP is also supported for the HPSDR version of PowerSDR.

How does the HiQSDR, SDR-IQ, and Hermes-Lite fit into the competitive receiver-exciter domain?  If they are “acceptable”, I think the RP is pretty close to them.  (I’m really asking to get a better feel for where it should fit in the SDR world.  I don’t intend to be frivolous)
73, Terry, N4TLF 


From: Graham / KE9H 
Sent: Thursday, December 17, 2015 7:18 PM
To: Helmut 
Cc: Terry Fox ; HPSDR 
Subject: Re: [hpsdr] FW: SBC Inforce 6410

I agree that the Red Pitaya is a great price for a flexible piece of test equipment.

And it might be a great starting point for a low cost transceiver, but I don't know yet.

I would like the receiver to get all of the performance it could, out of that A->D converter.


To be a competitive receiver-exciter, I am concerned about

1.) The loss in input NF because of the oscilloscope input versus a properly designed 50 Ohm input.

2.) Lack of appropriate Nyquist filters.

3.) The poor frequency stability of the on-board sampling clock.

4.) The poor phase noise performance of the on-board sampling clock.

5.) Moving the sampling clock to the telecom frequency ladder, ie., 122.88 MHz


I don't know that all of these are issues, just what I am worried about, and would need to verify/test.

I am making assumptions as to how they implemented the oscilloscope inputs, and could easily be wrong.


When I say poor, I don't mean that the Red Pitaya is not good for its intended purpose, which I am

sure that it is, but poor relative to the performance I personally expect out of an SDR.


It might be possible to hack in a different front end connection to deal with (1 and 2).


It might be possible to hack in a better external sampling reference clock, that would deal with (3, 4, and 5).


I am sure that you would need at least 6 layer board, maybe 8 layers to interface to the Zync BGA, so

a re-layout would not be trivial.


I am very interested in what Terry finds out about the LF spurs.


Thanks,

--- Graham

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