[hpsdr] FW: SBC Inforce 6410

[Graham / KE9H]

I agree that the Red Pitaya is a great price for a flexible piece of test
equipment.
And it might be a great starting point for a low cost transceiver, but I
don't know yet.
I would like the receiver to get all of the performance it could, out of
that A->D converter.

To be a competitive receiver-exciter, I am concerned about
1.) The loss in input NF because of the oscilloscope input versus a
properly designed 50 Ohm input.
2.) Lack of appropriate Nyquist filters.
3.) The poor frequency stability of the on-board sampling clock.
4.) The poor phase noise performance of the on-board sampling clock.
5.) Moving the sampling clock to the telecom frequency ladder, ie., 122.88
MHz

I don't know that all of these are issues, just what I am worried about,
and would need to verify/test.
I am making assumptions as to how they implemented the oscilloscope inputs,
and could easily be wrong.

When I say poor, I don't mean that the Red Pitaya is not good for its
intended purpose, which I am
sure that it is, but poor relative to the performance I personally expect
out of an SDR.

It might be possible to hack in a different front end connection to deal
with (1 and 2).

It might be possible to hack in a better external sampling reference clock,
that would deal with (3, 4, and 5).

I am sure that you would need at least 6 layer board, maybe 8 layers to
interface to the Zync BGA, so
a re-layout would not be trivial.

I am very interested in what Terry finds out about the LF spurs.

Thanks,
--- Graham

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