F.Y.I. "As FPGA designs employ very fast I/Os and bidirectional data buses, it becomes a challenge to verify correct timing of valid data within setup time and hold time. Floor planning enables resources allocation within FPGAs to meet these time constraints." <URL: https://en.wikipedia.org/wiki/Field-programmable_gate_array > 72/73 Ken -- ¯\_(ツ)_/¯