[hpsdr] "FPGA Floor Planning"

[Joe Martin]

Hi Ken, 

Yes, thanks!  Phil and I have learned by experience with our timing efforts how tricky it is to handle fast, wide data buses in the FPGA with regard to achieving suitable timing constraints.  Unfortunately, the floor planning option is not a feature that is available in the free versions of Quartus and we are reluctant to move toward a paid subscription of Quartus as that would be inconsistent with the “open” nature of the HPSDR projects.  So, even though it is harder to work with the free versions that don’t have the nice features available in paid subscription versions we’ve decided to keep to the free versions so anyone in the community can work with the firmware if they desire to do so. 

73, Joe K5SO

> On Feb 10, 2017, at 7:12 AM, Ken N9VV <n9vv at wowway.com> wrote:
> 
> ***** High Performance Software Defined Radio Discussion List *****
> 
> F.Y.I.
> 
> "As FPGA designs employ very fast I/Os and bidirectional data buses, it becomes a challenge to verify correct timing of valid data within setup time and hold time. Floor planning enables resources allocation within FPGAs to meet these time constraints."
> 
> <URL: https://en.wikipedia.org/wiki/Field-programmable_gate_array
> >
> 
> 72/73 Ken