[hpsdr] filtering options in FPGA

[k3it]

Hi Phil

On Sat, Sep 21, 2013 at 11:21 PM, Phil Harman <phil at pharman.org> wrote:

>   I’d estimate about 5 mins work + compile time.
>

Sounds easy, I should be done in about a month then :)

I think this line needs to be replaced with something that casts 18 bit
samples from CIC to 24 bit out_data_I2/Q2 and may be double the decimation
rate in filter "B"

firX8R8 fir2 (clock, decimB_avail, decimB_real, decimB_imag, out_strobe,
out_data_I2, out_data_Q2);


 My personal preference is to send raw ADC samples to the PC, or a
> dedicated single board computer (SBC), and do ALL the processing there [image:
> Smile].
>

 I wonder if the FPGA can do real time data compression so that all data
fits into 1 Gbit.  I guess about 3x-4x compression ratio would be needed at
close too 300 MB/s rate.  Or is there a better way?

Hope you are feeling better!

73
Vasiliy


>
>  *From:* k3it <gokoyev+k3it at gmail.com>
> *Sent:* Sunday, September 22, 2013 10:32 AM
> *To:* HPSDR list <hpsdr at lists.openhpsdr.org>
> *Subject:* [hpsdr] filtering options in FPGA
>
> ***** High Performance Software Defined Radio Discussion List *****
>
>  ------------------------------
> Does anybody know how big of an effort would be to modify the current
> Hermes firmware to send the RX streams after the CIC filters and exclude
> all FIR processing?   I'd like to run an experiment with implementing a
> decimating FIR filter on the PC.
>
> For example I'd like CIC decimate to 384k in FPGA and then CFIR decimate
> by 4 on the PC to get 96k finished spectrum.  is there anything wrong with
> this approach?
>
> I want to do this for two reasons
> - get feet wet with Verilog
> - see how much FPGA space can be recovered by moving part of the
> processing to the PC
>
> --
> 73! Vasiliy K3IT
>
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