[hpsdr] filtering options in FPGA

[Phil Harman]

Hi Vasiliy,

Nothing wrong with that approach. You will need to set the sampling rate in the C&C bits to 96k even though the data is being sent at 384k.  I’d estimate about 5 mins work + compile time. 

The Polyphase FIR in the FPGA is quite efficient in terms of  number of gates it uses so I’m not sure you will save much in the way of space.

We do something similar on Tx i.e. the FIR is done in the PC and the CIC interpolating filters are in the FPGA.

My personal preference is to send raw ADC samples to the PC, or a dedicated single board computer (SBC), and do ALL the processing there .

A very interesting experiment, let us know how you go.

73 Phil....VK6PH



From: k3it 
Sent: Sunday, September 22, 2013 10:32 AM
To: HPSDR list 
Subject: [hpsdr] filtering options in FPGA

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Does anybody know how big of an effort would be to modify the current Hermes firmware to send the RX streams after the CIC filters and exclude all FIR processing?   I'd like to run an experiment with implementing a decimating FIR filter on the PC. 

For example I'd like CIC decimate to 384k in FPGA and then CFIR decimate by 4 on the PC to get 96k finished spectrum.  is there anything wrong with this approach?

I want to do this for two reasons 

- get feet wet with Verilog 
- see how much FPGA space can be recovered by moving part of the processing to the PC

-- 
73! Vasiliy K3IT


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